The present invention relates to a semiconductor memory device, and more particularly, to an internal voltage discharge circuit capable of efficiently adjusting a discharge amount of internal voltage depending on a potential of external power supply voltage applied to the memory device, and its control method.
In general, a semiconductor memory device generates a power supply voltage having a level as needed, from an external power supply voltage having less than a certain level, for its use therein. For a memory device with a bit line sense amplifier such as DRAM, a core voltage VCORE is used to amplify cell data. When word lines are activated, data in plural memory cells coupled to the word lines are conveyed to a pair of bit lines. Then, the bit line sense amplifier senses and amplifies a voltage difference between the pair of bit lines.
In this manner, the DRAM uses the core voltage, and is provided with an internal driver, i.e., a core voltage driver for generating a core voltage level. By the way, as the DRAM operates at a high speed more and more, cells should also operate at a high speed and thus a core voltage level of cells also needs fast charging capability. Here, the charging means that data (voltage) loads on a capacitor within the DRAM.
Thus, an overdriving method has been used to generate a core voltage level at an external power supply voltage VDD level that is a higher potential than it, and amplify data at the core voltage level. Also, a release driver has been utilized to discharge the core voltage level in order to prevent the core voltage level from being kept in high state by such overdriving even after the overdriving operation.
As noted above, the voltages used for the semiconductor memory device are divided into the external power supply voltage and the internal voltage such as the core voltage generated by using the external power supply voltage. The internal voltage may easily vary by an internal operation of the semiconductor memory device. Particularly, there may be a possibility that the internal voltage contacts with a voltage having a higher level than its own voltage level, or if two or more voltages share the same node, there may be a difference between values of the shared voltages and a preset voltage. This phenomenon may frequently occur between the external power supply voltage and the core voltage in operation of the semiconductor memory device.
FIG. 1 is a diagram showing a general sense amplifier, and FIGS. 2 and 3 are circuit diagrams showing a controller for a sense amplifier power line.
Referring to FIGS. 1 to 3, the sense amplifier 10 uses power supply voltages RTO and SB to sense and amplify a level difference of both bit lines BL and /BL. For sensing operation, a core voltage VCORE should be applied to an RTO terminal, while a ground voltage VSS should be applied to an SB terminal.
In order that the semiconductor memory device has good operation characteristics tRCD by fast sensing, an external power supply voltage VDD is applied to the RTO terminal during a high pulse interval of an RT01 signal as shown in FIG. 4. That is, when the RTO1 signal is at logic high level, a PMOS transistor MP1 is turned on, thereby supplying the external power supply voltage VDD to the RTO terminal.
On the other hand, when the RTO1 signal becomes a logic low level, the PMOS transistor MP1 is turned off, thereby preventing the external power supply voltage VDD from being supplied to the RTO terminal. At this time, an RTO2 signal is also enabled to a logic high level and thus the PMOS transistor MP2 is turned on, thereby changing the power supply voltage applied to the RTO terminal from the external power supply voltage VDD to the core voltage VCORE.
For this operation, a core voltage overdriving circuit is configured such that the RTO node rising to the VDD level during an overdriving interval is coupled to the core voltage VCORE to bypass current to the VCORE node, so that the VCORE level rises.
That is, the core voltage level rises due to current inflow by the external power supply voltage VDD applied to the RTO terminal during the overdrive interval, as shown in FIG. 4. At this time, the core voltage level becomes higher than a target voltage, and thus there is a need for the control of discharging the raised core voltage level so as to return it to a predetermined target core voltage level.
FIG. 5 is an existing internal voltage discharge circuit to return a core voltage that was higher than a target level to a target level by its discharging.
In the existing internal voltage discharge circuit, a drive point of time is determined by an enable signal VCR_ON that has a logic high level in synchronism with a falling edge of the RTO1 signal. Such an internal voltage discharge circuit operates during an interval where the enable signal is at a logic high level, wherein the operation interval has about several tens of nanoseconds.
The existing internal voltage discharge circuit is configured in a manner that a reference voltage VREFC for generating a core voltage is coupled to an NMOS transistor N1 located at an input end of a differential comparator and a feedback voltage VCORE/2 (HFVCORE) is coupled to an NMOS transistor N2 located at another input end of the differential comparator. By this configuration, the core voltage level can be kept at a stable level twice the internal reference voltage VREFC.
Thus, when the enable signal VCR_ON becomes a logic high level, a high level signal is applied to a gate of an NMOS transistor N3 to control the differential comparator to be operable. The differential comparator serves to compare the feedback voltage having a level of VCORE/2 voltage-divided by transistors N9 and N10 having diode characteristics with the reference voltage.
However, in case where the level of the core voltage end rises over the target level by the overdriving control method as shown in FIG. 4, the feedback voltage has a higher potential than the reference voltage. At this time, more current flows through the NMOS transistor N2, so that the electric potential of the node B drops.
As the electric potential of the node B is decreased, the gate voltage of a PMOS transistor P4 is also decreased. This increases a drive force of the PMOS transistor P4, which raises the electric potential of the node E. And the raised voltage of the node E turns on discharge transistors N7 and N8, thereby discharging the core voltage.
Meanwhile, the internal voltage discharge circuit is affected by the level of the external power supply voltage during the overdriving control process, as shown in FIGS. 2 and 3.
FIG. 6 is a diagram showing characteristics in which the amount of external power supply voltage VDD applied to a core voltage end varies depending on a level of the external power supply voltage VDD. When the external power supply voltage VDD is in a high level (HIGH VDD) state, more current flows to further raise the potential of the core voltage, compared to when it is at a normal level. On the other hand, when the external power supply voltage VDD is in a low level (LOW VDD) state, a relatively small current flows which lets the potential of the core voltage rise less, compared to when it is at a normal level.
Although the potential of the core voltage varies depending on the level of the external power supply voltage, the amount of discharge of the core voltage does not vary in a remarkable way. This is because the discharge transistors N7 and N8 operate regardless of level variation of the external power supply voltage. Therefore, when the external power supply voltage is at a logic high level HIGH VDD, a discharge amount by the discharge transistors is nothing but very small. Thus, much time is taken to let the core voltage drop to a target level, so that a sufficient discharge cannot occur. On the contrary, when the external power supply voltage is at a logic low level LOW VDD, a sufficient amount of discharge has been already made, but such a discharge operation is continuously performed, thereby rendering the core voltage lower than the target level. That is, since the conventional internal voltage discharge circuit does not efficiently use current, it increases current consumption.